Registers
| offset | name | access | size | description | |
| 0x00 | TXT.ACCESS | RO | 32 | TPM/TXT access control register (chipset-specific) | |
| 0xA0 | TXT.BOOTSTATUS | RO | 32 | Bootstatus/flags for startup function execution. | |
| 0x110 | TXT.DIDVID | RO | 64 | Device/vendor/revision ID for memory controller/chipset. | |
| 0x200 | TXT.VER.EMIF | RO | 32 | EMC/version register identifying debug or production fuse state. | |
| 0x218 | TXT.CMD.UNLOCK-MEM-CONFIG | WO | 8 | Command to unlock memory configuration registers. | |
| 0x270 | TXT.SINIT.BASE | RW | 32 | Physical base address for SINIT AC module region. | |
| 0x278 | TXT.SINIT.SIZE | RW | 32 | Size (bytes) of SINIT AC module region. | |
| 0x290 | TXT.MLE.JOIN | RW | 32 | Physical address pointer to MLE JOIN data structure. | |
| 0x300 | TXT.HEAP.BASE | RW | 32 | Physical base address of the TXT heap memory region. | |
| 0x308 | TXT.HEAP.SIZE | RW | 32 | Size (bytes) of the TXT heap memory region. | |
| 0x328 | TXT.ACM_ERROR_STATUS | RO | 32 | ACM error/status register (pre-boot error codes). | |
| 0x330 | TXT.DPR | RW | 32 | DMA Protected Range register (defines DPR size/top and lock bit). | |
| 0x378 | TXT.SCRATCHPAD/ACM_POLICY_STATUS | RO/RW | 64 | ACM policy/status scratchpad (TPM type | startup info). |
| 0x380 | TXT.CMD.OPEN.LOCALITY1 | WO | 8 | Command to open TPM locality 1 (enable chipset decoding). | |
| 0x388 | TXT.CMD.CLOSE.LOCALITY1 | WO | 8 | Command to close TPM locality 1. | |
| 0x390 | TXT.CMD.OPEN.LOCALITY2 | WO | 8 | Command to open TPM locality 2 (auto-opened after SENTER). | |
| 0x398 | TXT.CMD.CLOSE.LOCALITY2 | WO | 8 | Command to close TPM locality 2. | |
| 0x400 | TXT.PUBLIC.KEY | RO | 256 | AC module public key hash (deprecated on some platforms). | |
| 0x810 | TXT.DIDVID2 | RO | 64 | Alternate device ID register (device/vendor/revision). | |
| 0x8E0 | TXT.CMD.SECRETS | WO | 8 | Set secrets sticky command (indicates secrets in memory). | |
| 0x8E8 | TXT.CMD.NO-SECRETS | WO | 8 | Clear secrets command (indicates no secrets in memory). | |
| 0xE00 | TXT.E2STS | RO | 32 | Extended error/status register (chipset-specific) | |
| 0xF00 | TXT.CMD. |
RW | 32 | Additional vendor/chipset-specific commands and status registers |
This project is an independent, unofficial work based on publicly available information and reverse-engineering research, and is not affiliated with, endorsed by, sponsored by, or associated with Intel Corporation or its affiliates. It is provided "as is", without warranty of any kind. The author assumes no responsibility or liability for any use, misuse, damage, data loss, hardware failure, or other consequences arising from its use. Intel, Pentium, Core and related trademarks are the property of their respective owners and are used solely for identification and informational purposes.