Table of contents

SIGEVENT

Purpose: Drive fault_info bus with exception/event data

Operation: fault_info = src1[7:0]; result = src2

Flags: 0

Likely:

SIGEVENT(vector, condition)

Usage with UOP.120

UOP.120 probably prepares resulting variable for exception

TMP6 =         UOP.120        (CONST.16.006  , CONST.16.006  )
EOM.Fl2                   SIGEVENT       (TMP6          , CONST.16.001  , U4.00000001 /* U4:0000 0000 0000 0000 0000 0000 0000 0001 */)

Exception list

Name Vector nr. Type Mnemonic Error code?
Division Error 0 (0x0) Fault #DE No
Debug 1 (0x1) Fault/Trap #DB No
Non-maskable Interrupt 2 (0x2) Interrupt - No
Breakpoint 3 (0x3) Trap #BP No
Overflow 4 (0x4) Trap #OF No
Bound Range Exceeded 5 (0x5) Fault #BR No
Invalid Opcode 6 (0x6) Fault #UD No
Device Not Available 7 (0x7) Fault #NM No
Double Fault 8 (0x8) Abort #DF Yes (Zero)
Coprocessor Segment Overrun 9 (0x9) Fault - No
Invalid TSS 10 (0xA) Fault #TS Yes
Segment Not Present 11 (0xB) Fault #NP Yes
Stack-Segment Fault 12 (0xC) Fault #SS Yes
General Protection Fault 13 (0xD) Fault #GP Yes
Page Fault 14 (0xE) Fault #PF Yes
Reserved 15 (0xF) - - No
x87 Floating-Point Exception 16 (0x10) Fault #MF No
Alignment Check 17 (0x11) Fault #AC Yes
Machine Check 18 (0x12) Abort #MC No
SIMD Floating-Point Exception 19 (0x13) Fault #XM/#XF No
Virtualization Exception 20 (0x14) Fault #VE No
Control Protection Exception 21 (0x15) Fault #CP Yes
Reserved 22-27 (0x16-0x1B) - - No
Hypervisor Injection Exception 28 (0x1C) Fault #HV No
VMM Communication Exception 29 (0x1D) Fault #VC Yes
Security Exception 30 (0x1E) Fault #SX Yes
Reserved 31 (0x1F) - - No
Triple Fault - - - No
FPU Error Interrupt IRQ 13 Interrupt #FERR No

Usage in CPUID MSROM 6D8

(CPUID 652 is similar)

BOM_Fl3                   SIGEVENT       (R36           , CONST_16_081  , UP3_01)
EIP_30 =       SIGEVENT       (R34           , CONST_16_05C  , U2_28)
EIP_30 =       SIGEVENT       (TMP2          , CONST_16_05C  , U2_28)
EIP_30 =       SIGEVENT       (TMP3          , CONST_16_05C  , U2_20)
EIP_30 =       SIGEVENT       (TMP3          , CONST_16_05C  , U2_28)
EIP_30 =       SIGEVENT       (TMPA          , CONST_16_05C  , U2_28)
EOM_Fl2                   SIGEVENT       (R36           , CONST_16_081  )
EOM        TMPB =         SIGEVENT       (TMPA          , TMPB          , U2_08)
_Fl2_Fl3   REG_4C =       SIGEVENT       (CONST_00_100  , TMP3          , UP3_01)
_Fl2_Fl3                  SIGEVENT       (TMP1          , CONST_16_0E7  )
_Fl2_Fl3                  SIGEVENT       (TMP3          , CONST_16_0E7  )
_Fl2                      SIGEVENT       (CONST_16_07A  , CONST_16_07A  , U2_28)
_Fl2                      SIGEVENT       (TMP0          , CONST_16_001  , UP3_01)
_Fl2                      SIGEVENT       (TMP0          , CONST_16_041  , UP3_09)
_Fl2                      SIGEVENT       (TMP6          , CONST_16_001  )
_Fl2                      SIGEVENT       (TMP7          , CONST_16_0C1  , U2_20)
REG_4C =       SIGEVENT       (CONST_00_100  , TMP3          )
REG_5C =       SIGEVENT       (CONST_00_100  , TMP5          )
SIGEVENT       (CONST_16_005  , CONST_16_005  )
SIGEVENT       (CONST_16_009  , CONST_16_009  )
SIGEVENT       (CONST_16_062  , CONST_16_062  , U2_08)
SIGEVENT       (CONST_16_07A  , CONST_16_07A  , U2_08)
SIGEVENT       (CONST_16_0AB  , CONST_16_0AB  , U2_08)
SIGEVENT       (CONST_16_0CC  , CONST_16_0CC  , U2_28)
SIGEVENT       (CONST_16_0CC  , CONST_16_0CC  , U2_28, U3_40)
SIGEVENT       (R36           , CONST_16_001  , U2_20)
SIGEVENT       (TMP0          , TMP1          )
SIGEVENT       (TMP0          , TMP2          )
SIGEVENT       (TMP0          , TMP2          , U2_08)
SIGEVENT       (TMP3          , CONST_16_001  )
SIGEVENT       (TMP3          , CONST_16_0E7  )
SIGEVENT       (TMP3          , CONST_16_0E7  , UP3_01)
SIGEVENT       (TMP3          , CONST_16_0E7  , UP3_05)
SIGEVENT       (TMP4          , TMP3          )
SIGEVENT       (TMP4          , TMP5          )
SIGEVENT       (TMP5          , TMP4          )
SIGEVENT       (TMP5          , TMP7          )
SIGEVENT       (TMP6          , TMP7          )
SIGEVENT       (TMPA          , TMPB          )
SIGEVENT       (TMPA          , TMPB          , U2_08)
SIGEVENT       (TMPB          , TMPA          )

References

This project is an independent, unofficial work based on publicly available information and reverse-engineering research, and is not affiliated with, endorsed by, sponsored by, or associated with Intel Corporation or its affiliates. It is provided "as is", without warranty of any kind. The author assumes no responsibility or liability for any use, misuse, damage, data loss, hardware failure, or other consequences arising from its use. Intel, Pentium, Core and related trademarks are the property of their respective owners and are used solely for identification and informational purposes.
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