Table of contents

Modifiers

Core2 issue

References

Store address + execute phase for memory access.

Stores value stored by previous STRD call to specified memory location.

Example

STRD           (CONST_0       , TMP4          )
STA.M0.SC1.DSZ32(CONST_04+1FC  , ESP_20        , SS      , OA.8, U2.08)

Modifiers

E.g. STA.M0.SC1.DSZ32

SC modifier

Selects store-cache port number. Probably.

DSZ Modifier

DSZ8,DSZ16,DSZ32, DSZ64

Core2 issue

Core2 has sometimes DSZ modifier with value 180 (e.g. ADD.180, which seems to be similar to DSZ32)

Push on stack example (Pentium-M 6D8)

STA.SC1.DSZ32  (CONST_04+1FC  , ESP_20        , SS      , OA_8, U2_08)
ESP_20 =   SUB.DSZ16      (ESP_20        , CONST_16+004  , OA_4)

A bit mysterious combination with STRD (utool MSROM reader):

UROM_3FC0	STA40_SC1_DSZ32(CONST_06_000  , TMP0           , LINSEG   )
UROM_3FC1	TMP0 = ADD_DSZ32       (TMP0          , CONST_16_004   )

References

US5699085 (ROB / store buffer design)
US6510276 (store pipeline, memory ports)

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