Slot 1

Pinout

Pin#	Signal-Name	Pin#	Signal-Name
A1	VCC1.5	B1	RSVD5-EMI
A2	GND	B2	FLUSH#
A3	VCC1.5	B3	SMI#
A4	IERR#	B4	INIT#
A5	A20M#	B5	VCC1.5
A6	GND	B6	STPCLK#
A7	FERR#	B7	TCK
A8	IGGNE#	B8	SLP#
A9	TDI	B9	VCC1.5
A10	GND	B10	TMS
A11	TD0	B11	TRST#
A12	PWRGD	B12	RESERVED-UP#
A13	RSVD-TESTHI	B13	VCC CORE
A14	GND	B14	RSVD2-THRMDP
A15	THERMTRIP#	B15	RSVD-THRMDN
A16	RSVD	B16	LINT1#
A17	LINT0#	B17	VCC CORE
A18	GND	B18	PICCLK
A19	PICD0	B19	BP2#
A20	PREQ#	B20	RSVD-TESTHI
A21	BP3#	B21	100/66# MHz
A22	GND	B22	PICD1
A23	BPMO#	B23	PRDY#
A24	BINIT#	B24	BPM1#
A25	DEP0#	B25	VCC CORE
A26	GND	B26	DEP2#
A27	DEP1#	B27	DEP4#
A28	DEP3#	B28	DEP7#
A29	DEP5#	B29	VCC CORE
A30	GND	B30	D62#
A31	DEP6#	B31	D58#
A32	D61#	B32	D63#
A33	D55#	B33	VCC CORE
A34	GND	B34	D56#
A35	D60#	B35	D50#
A36	D53#	B36	D54#
A37	D57#	B37	VCC CORE
A38	GND	B38	D59#
A39	D46#	B39	D48#
A40	D49#	B40	D52#
A41	D51#	B41	EMI2
A42	GND	B42	D41#
A43	D42#	B43	D47#
A44	D45#	B44	D44#
A45	D39#	B45	VCC CORE
A46	GND	B46	D36#
A47	RSVD1	B47	D40#
A48	D43#	B48	D34#
A49	D37#	B49	VCC CORE
A50	GND	B50	D38#
A51	D33#	B51	D32#
A52	D35#	B52	D28#
A53	D31#	B53	VCC CORE
A54	GND	B54	D29#
A55	D30#	B55	D26#
A56	D27#	B56	D25#
A57	D24#	B57	VCC CORE
A58	GND	B58	D22#
A59	D23#	B59	D19#
A60	D21#	B60	D18#
A61	D16#	B61	EMI3
A62	GND	B62	D20#
A63	D13#	B63	D17#
A64	D11#	B64	D15#
A65	D10#	B65	VCC CORE
A66	GND	B66	D12#
A67	D14#	B67	D7#
A68	D9#	B68	D6#
A69	D8#	B69	VCC CORE
A70	GND	B70	D4#
A71	D5#	B71	D2#
A72	D3#	B72	D0#
A73	D1#	B73	VCC CORE
A74	GND	B74	RESET#
A75	BCLK#	B75	BREQ1#
A76	BREQ0#	B76	FRCERR#
A77	BERR#	B77	VCC CORE
A78	GND	B78	A35
A79	A33	B79	A32
A80	A34	B80	A29
A81	A30	B81	EMI4
A82	GND	B82	A26
A83	A31	B83	A24
A84	A27	B84	A28
A85	A22	B85	VCC CORE
A86	GND	B86	A20
A87	A23	B87	A21
A88	RSVD0	B88	A25
A89	A19	B89	VCP
A90	GND	B90	A15
A91	A18	B91	A17
A92	A16	B92	A11
A93	A13	B93	VCC CORE
A94	GND	B94	A12
A95	A14	B95	A8
A96	A10	B96	A7
A97	A5	B97	VCC CORE
A98	GND	B98	A3
A99	A9	B99	A6
A100	A4	B100	RSVD-EMI
A101	BNR#	B101	SLOTOC#
A102	GND	B102	REQ0#
A103	BPRI#	B103	REQ1#
A104	TRDY#	B104	REQ4#
A105	DEFER#	B105	VCC CORE
A106	GND	B106	LOCK#
A107	REQ2#	B107	DRDY#
A108	REQ3#	B108	RSO#
A109	HITM#	B109	VCC5
A110	GND	B110	HIT#
A111	DBSY#	B111	RS2#
A112	RS1#	B112	RSVD
A113	RSVD	B113	VCC3
A114	GND	B114	RP#
A115	ADS#	B115	RSP#
A116	RSVD3	B116	AP1#
A117	AP0#	B117	VCC3
A118	GND	B118	AERR#
A119	VID2	B119	VID3
A120	VID1	B120	VID0
A121	VID4	B121	VCC3

BF[0:3] CPU-Bus ratio settings

CPU             Bus
Frequ.          Clock
MHz    Ratio    MHz     BF0  BF1  BF2  BF3
---------------------------------------------
233    3.5x     66       0    0    1    1
266    4.0x     66       1    1    0    1
300    4.5x     66       0    1    0    1
333    5.0x     66       1    0    0    1
350    3.5x    100       0    0    1    1
400    4.0x    100       1    1    0    1
450    4.5x    100       0    1    0    1
500    5.0x    100       1    0    0    1
550    5.5x    100       0    0    0    1

VID

VID4	VID3	VID2	VID1	VID0	VCCCORE
A121	B119	A119	A120	B120
0	0	1	0	1	1.80
0	0	1	0	0	1.85
0	0	0	1	1	1.90
0	0	0	1	0	1.95
0	0	0	0	1	2.00	(default	P2)
0	0	0	0	0	2.05
1	1	1	1	1	No	Core
1	1	1	1	0	2.10
1	1	1	0	1	2.20
1	1	1	0	0	2.30
1	1	0	1	1	2.40

"0" means: "closed internally" or "logic low" or "short to ground"

"1" means: "open" or "logic high" or "NOT short to ground"

Adapters from Socket 370

PII CPU CARD ver 1.5

JP1 FSB, open 66MHz, closed overclock,

JP2 dual processing, open none, closed dual.

References

web.archive.org/.../http://www4.tomshardware.com/cpu/19981215/index.html↗

This project is an independent, unofficial work based on publicly available information and reverse-engineering research, and is not affiliated with, endorsed by, sponsored by, or associated with Intel Corporation or its affiliates. It is provided "as is", without warranty of any kind. The author assumes no responsibility or liability for any use, misuse, damage, data loss, hardware failure, or other consequences arising from its use. Intel, Pentium, Core and related trademarks are the property of their respective owners and are used solely for identification and informational purposes.