Table of contents

Just some random unsorted papers

General

key08.com/usr/uploads/2022/04/1807572259.pdf↗
intel.com/.../documents/research/2001-vol05-iss-1-intel-technology-journal.pdf↗
www.cl.cam.ac.uk/teaching/0405/CompArch/Gwennap95-P6_Microarchitecture.pdf↗
dspace.mit.edu/.../4E0FC5FE-6F01-43D7-95FE-91E32EB349CF/0/lecture20.pdf↗
www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html↗ (Intel IA32 SDM)
uops.info/table.html↗
Hennessy & Patterson — Computer Architecture: A Quantitative Approach ( Defines MAR, MDR, RAT, ROB, scoreboard, issue queues)
Robert P. Colwell, The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips (Practitioners)
John Paul Shen, Mikko H. Lipasti, Modern Processor Design Fundamentals Of Superscalar Processors archive.org/.../modern-processor-design-fundamentals-of-superscalar-proce....com↗
Jon Stokes “Inside the Machine”

ARCHITECTURE AND PERFORMANCE PAPERS

David Papworth, “Tuning the Pentium Pro Microarchitecture,” 1996.
Dileep Bhandarkar and Jason Ding, “Performance Characterization of the Pentium Pro Processor,” 1997.
Linley Gwennap, “Intel’s P6 Uses Decoupled Superscalar Design,” 1995.
Linley Gwennap, “New Algorithm Improves Branch Prediction,” 1995.
Robert Colwell and Randy Steck, “A 0.6 µm BiCMOS Processor with Dynamic Execution,” 1995. We have the presentation slides, but not the original proceedings paper.
Intel, “Intel Presents P6 Microarchitecture Details,” 1995.
Intel, “The P6 Architecture: Background Information for Developers,” 1995.
Intel, “Dynamic Execution Explanation,” 1995.
Intel, “A Tour of the P6 Microarchitecture,” 1995.
Intel Technology Journal, Q3 1997 — MMX and Pentium II material.

Intel patents

US5559974 — Decoder expansion using independently loaded micro-alias and macro-alias registers
US5721855 — Integrated speculative pipeline and reorder buffer
US5627985 — Speculative and committed resource files; register renaming and retirement
US6047369 — Flag renaming and partial flag updates
US5689674 — Reservation-station dispatch and execution-port assignment
US5694553 — Buffered-load dispatch readiness and memory-ordering checks
US5577217 — Two-level branch target buffer
US6026477 — Branch-misprediction recovery

(the below patents are nonsense made by LLM by compacting a conversation with real documents, I need to look this up manually and sort out all AMD stuff)

US6045385 Microcode sequencer design
US5542460 Branch prediction
US5588162 Internal instruction scheduling
US5699085 Reorder buffer and rename
US6510276 Execution pipeline

Misc hardware

www.vogons.org/viewtopic.php?p=1307671#p1307671↗ (Pentium Pro to Slot 1)
github.com/x86-JTAG-Open-Research/x86-JTAG-Information↗ x86 JTAG
rayer.g6.cz/hardware/lpc2isa.htm↗ LPC to ISA

Microinstructions

github.com/sladen/intel-microcode/blob/master/micro-instructions.txt↗
phg.chat.ru/opcode.txt↗
www.fermimn.edu.it/inform/materiali/evarchi/intel/p6/optimgd.pdf↗ (v2.2 1995-04)
datasheets.chipdb.org/Intel/x86/P6/optimgd.pdf↗
wasm.in/threads/kolichestvo-taktov-na-komandu.1410/page-2↗
kib.kiev.ua/x86docs/Intel/Intel-OptimGuide/242816-001.pdf↗ (AP-526, 1995-10)
patents.google.com/patent/US6934828↗ fp_store_address fp_store_data
blog.can.ac/2021/03/22/speculating-x86-64-isa-with-one-weird-trick/↗
intel.com/.../documents/research/1999-vol03-iss-2-intel-technology-journal.pdf↗
bebop.cs.berkeley.edu/.../arch-manuals/pentium-iii/keshava99-impltradeoffs.pdf↗

General books

Hennessy, John L.; Patterson, David A. (2017). ''Computer Architecture: A Quantitative Approach'' (6th ed.). Morgan Kaufmann. ISBN 978-0128119051.
Shen, John P.; Lipasti, Mikko H. (2013). ''Modern Processor Design: Fundamentals of Superscalar Processors'' (2nd ed.). Waveland Press. ISBN 978-1478601043.
Johnson, Mike (1991). ''Superscalar Microprocessor Design''. Prentice Hall. ISBN 978-0138756349.
Baer, Jean-Loup (2010). ''Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors''. Cambridge University Press. ISBN 978-0521769921.
Sima, Dezső; Fountain, Terence; Kacsuk, Péter (1997). ''Advanced Computer Architectures: A Design Space Approach''. Addison-Wesley. ISBN 978-0201422917.

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