Table of contents

Architectural integer registers

EAX,EBX, etc.

REG_ddd is aliased destination operand (taken from x86 instruction opcode)

REG_sss is aliased source operand (taken from x86 instruction opcode)

FPU special registers

TMPn are mainly used for FPU operation

Unknown:

REG.21

REG.23

REG.F2

XMM register set

Introduced on Pentium M (9th bit of register index). Earlier processors do not utilize this extended register set.

Accessed in 64bit parts as low and high (XMM0L, XMM0H, etc.)

XMM0..7 -> so total 8x2 64-bit registers

REG_xmm_dddP (where P is L or H) is aliased destination operand (taken from x86 SSE2 instruction opcode)

REG_xmm_sssP (where P is L or H) is aliased source operand (taken from x86 SSE2 instruction opcode)

Temporary registers

TMP0..n ; these registers seems to be versatile, as they can hold even floating point numbers or 64bit values even on all P6 processors (even 32-bit!).

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