Table of contents

Probe Mode

Probe Mode operation on the P6 is straightforward. To halt the processor, the PREQ# pin on the CPU is asserted. The CPU then responds by asserting PRDY#. x86 instructions are submitted one at a time to the Probe Instruction Register using the WRSUBPIR TAP command. These instructions allow modification of registers, access to memory, and communication with I/O devices.

For example, to write registers, the following x86 opcode can be placed into the Probe Instruction Register:

mov register, value_to_write

To write memory:

mov edx, memory_address
mov eax, value_to_write
mov [edx], eax

To write to an I/O port:

mov dx, io_address
mov ax, value_to_write
out dx, ax

To read registers and memory, the required data must first be moved into the EAX register. An RDMSR instruction is then issued targeting the PDR MSR. The READPDR TAP command is subsequently executed to shift the contents of the PDR out through the JTAG shift register.

For example, to read memory:

mov edx, memory_address
mov eax, [edx]
mov ecx, 71h
rdmsr

Execute READPDR TAP command

To read registers:

mov eax, register_to_read
mov ecx, 71h
rdmsr

Execute READPDR TAP command

Evolution

Pentium Probe Mode evolved significantly from the P5 to the P6. In the P6, the Probe Instruction Register no longer accepted microcode instructions; instead, it accepted x86 instructions. The Probe Data Register was no longer an internal register accessible only through microcode, but became available as an MSR.

The Probe Mode Control Register was moved from MSR address 8000001Dh to MSR 71h. Additionally, segment descriptor caches are accessed through MSRs in the P6 rather than through microcode addressing as in the P5. These Probe Mode MSRs are not accessible from Ring 0 and can only be accessed while in Probe Mode. Any attempt to read or write these MSRs from Ring 0 results in a General Protection Fault. Therefore, software protection mechanisms or anti-cheat rootkits cannot interfere with or detect Probe Mode operation.

Probe Mode changed very little from the P6 to the Pentium III. From the Pentium III to the Pentium M, the TAP protocol for reading the Probe Data Register was slightly modified. The Probe Instruction Register was changed to a fixed-length register (16 bytes) instead of the variable-length register used in the P6. The ODLAT (On-Die Logic Analyzer Trigger) feature was also added.

The Core 2 Duo family was derived from the Pentium M, so the Probe Mode implementation remained largely unchanged. The TAP protocol for reading the Probe Data Register was modified again, and additional TAP commands were introduced to support Hyper-Threading. For example, the THREADSELECT TAP command was added, allowing selection of which thread within a core to control.

However, one recent Intel processor architecture reverted to the P5-style implementation of Probe Mode: the Larrabee architecture, which is based on the P5. The u and v pipes of Intel Larrabee were extended by one bit each. New microcode instructions were introduced for Larrabee's FPU and vector extensions. Apart from these changes, the Probe Mode implementation is similar to the P5. The Probe Mode Control Register and Probe Data Registers are accessible only through microcode and are not exposed through MSRs.

Over successive x86 generations, Probe Mode became more powerful. Additional bits were added to the Probe Mode Control Register, allowing breakpoints on special processor transitions such as SMM entry/exit, C6 package entry/exit, CC1-CC7 entry/exit, VM entry/exit, and reset events.

Eventually, the Probe Mode Control Register no longer contained enough bits to control the increasing number of hooks and break conditions available in modern x86 processors. This led to the creation of Probe Mode Control Register 2 and the VM Probe Mode Control Register. Probe Mode Control Register 2 is suspected to control breaks on Intel TXT transitions, core and package power-state transitions, and VMX mode transitions, while the VM Probe Mode Control Register enables breaks on specific VM Exit conditions. It is unknown whether setting the Interrupt Redirect bit (bit 12) of DR7 is required for these break conditions to function.

Probe Mode Redirection

The probe mode redirection MSR 0x1DF allows to jump to ucode on many events (see CR_ICECTLPMR). The layout for Intel ATOM is following from Ermolov twitter:

Probe Mode redirection is a microcode feature of modern Intel CPUs allowing to halt CPU and jump into JTAG debugger due to many arch events. It's controlled by undocumented ICECTLPMR MSR (0x1DF). Here's its full layout for Atom Goldmont core:

Name="ir" Map="0:0"

Name="rsvd_1" Map="1:1"

Name="pmen" Map="2:2"

Name="pir" Map="3:3"

Name="is" Map="4:4"

Name="mce" Map="5:5"

Name="pm_redirect" Map="6:6"

Name="rsvd_7" Map="7:7"

Name="initen" Map="8:8"

Name="mchken" Map="9:9"

Name="smmenter" Map="10:10"

Name="smmexit" Map="11:11"

Name="rsvd_12" Map="12:12"

Name="prr" Map="13:13"

Name="pdr" Map="14:14"

Name="plr" Map="15:15"

Name="rem_in_pm" Map="16:16"

Name="rsvd_31_17" Map="31:17"

Name="cc1_entry_redirection_control" Map="32:32"

Name="cc2_entry_redirection_control" Map="33:33"

Name="cc3_entry_redirection_control" Map="34:34"

Name="cc4_entry_redirection_control" Map="35:35"

Name="cc5_entry_redirection_control" Map="36:36"

Name="cc6_entry_redirection_control" Map="37:37"

Name="rsvd_53_38" Map="53:38"

Name="intl" Map="54:54"

Name="step_into_exception" Map="55:55"

Name="shutdown" Map="56:56"

Name="vmclear_redirection_control" Map="57:57"

Name="vmexit" Map="58:58"

Name="rsvd_60_59" Map="60:59"

Name="stmservice" Map="61:61"

Name="osvvmentry" Map="62:62"

Name="vmlaunch" Map="63:63"

The MSR is acceptable itself only in Probe Mode (can be written by .msr OpenIPC command)

Tracing

For the Pentium M, an ODLAT (On-Die Logic Analyzer Trigger) feature was added. This feature provides three triggers that stop the processor when specific values appear on the processor bus. These triggers support don't-care values. Additionally, trigger C can be configured to become active only after trigger B has been activated, and trigger B can become active only after trigger A has been activated.

When these triggers fire, the processor toggles the BPM0, BPM1, and BPM2 pins depending on which trigger was activated. American Arium refers to this capability as a three-level bus analyzer breakpoint feature.

Starting with the Pentium 4 processor, an Extended Execution Trace feature was introduced. This allows the processor to emit packets over the BPM0-7 pins when special instructions or events occur. These include WRMSR, RDMSR, interrupts, I/O transactions, MWAIT transitions, and other events.

To enable Extended Execution Trace, special microcode patches must be applied through the BIOS microcode update mechanism. Similarly, special microcode patches can configure the BTM messages generated by the processor to include timestamps.

For the Pentium 4 only, there is a second type of Extended Execution Trace called Microcode Extended Execution Trace. This feature is suspected to allow the CPU to emit special packets on the BPM pins when specific microcode instructions are executed.

Pentium 4

PMCLRTHID Probe Mode P4 Spec.
PMENTER Probe Mode P4 Spec.
PMEXIT Probe Mode P4 Spec.
PMNOW Probe Mode P4 Spec.
PMSETHID Probe Mode P4 Spec.
READPDR0 Probe Mode P4 Spec.
READPDR1 Probe Mode P4 Spec.

Probe Mode

Details Operation

Evolution

Probe Mode Redirection

Tracing

Pentium 4

See also