TNS-UPP-NET
- 2. Technical description
- = 2.1 Standard part of UPP-NET (UPP-UNIVERSAL board) =
- = 2.2 Description of the connection of the UPP-NET application part =
- 3. Jumpers and switches
- 4. Map of I/O ports
- = 4.1 Internal CPU ports on the UPP-NET module =
- = 4.2 SIO ports key bits A control (0xEE) when read (RR0) =
- = 4.3 Standard UPP-NET addresses from the TNS bus side (host port) =
- 5. Shared SRAM map (view from host TNS)
- 6. Internal RAM Layout 0x4000–0x43FF
The description is based on the original documentation (popis_modulu_upp_net, uzivatelska_dok_upp_net) and on the reverse analysis of the firmware (ROM 2 KB, segment 0x0000–0x07FF); analysis of ROM UPP-NET and original documentation (Slušovice, approx. 1988).
Note: original documentation contains minor errors (8255 × PIO confusion, inconsistent
IO numbering) – below are the corrected values verified against the source code.
== 1. Principle of the == function
The UPP-NET module is used to connect TNS computers to a local LAN (Local Area Network). The maximum number of network participants is 64. TNS GC, TNS SC (when using the UPP-NET module) and TNS HC computers that already have a fast line interface on the motherboard can be connected in the network.
Data transfer between network participants takes place at the physical level in the SDLC synchronous protocol with an unmodulated signal and is controlled by the Z80-SIO integrated circuit. The data transmitted from the SIO is encoded in Manchester code and transmitted to the transmitter. The received data is processed in the receiver, decoded and fed to the SIO.
The operation of the entire system is controlled by a time base derived from a 10 MHz crystal. The galvanic isolation of the module from the line is ensured by a transformer coupling.
The Manchester code used makes it possible to encode the transmitter's clock signal, which is necessary for synchronous transmission, into the transmitted data. In addition, the signal coded in this way does not contain a DC component.
Each station on the line has its own user number, which is set on DIP-switches 1 to 6 of the SW1 switch field, where switch 1 corresponds to address order 0, etc. There must not be 2 stations with identical user numbers on one line.
= 2.1 Standard part of UPP-NET (UPP-UNIVERSAL board) =
The basic circuit of the card is a Z-80 microprocessor (IO 3). The CPU control program is stored in the EPROM memory (IO 4) in the address space 0 to 1000h. The data segment – RAM memory 1 kB – consists of two 2114 type circuits (IO 6, IO 7). The address space of the RAM is fixedly located from address 4000h and occupies a total of four duplicately addressed "kilos" (space 4000-5000h).
The standard part of the UPP-NET module also contains the Z80-PIO (IO 1) and Z80-CTC (IO 2) circuits, which in general are almost entirely usable for a specific application of the UPP type board.
Specifically, in the UPP-NET application, the CTC circuit is used only to ensure communication from the CPU of the TNS computer to the UPP-NET card (it ensures the generation of interrupts for the UPP module processor). The PIO circuit with gate "B" also participates in the communication of the UPP-NET card with the TNS processor – via bits 0 and 1 of this gate, the peripheral processor reads the state flags of the input and output buffers of the UPP-NET module. Gate "A" of the PIO circuit is used to identify the station number set on DIP switch SW1.
The PIO and CTC circuits are connected via their IEI inputs and IEO outputs into a priority interrupt chain, with CTC having the highest interrupt priority by default. In the case of the UPP-NET application, its IEI input is connected to the IEO output of the SIO circuit of the application part, so by default the SIO circuit has the highest interrupt priority.
Linear addressing is used to decode the IO1 (PIO) and IO2 (CTC) ports, so the PIO occupies the standard addresses F4 to F7h and the CTC circuit the addresses F8 to FBh. The SIO circuit of the UPP-NET application part has addresses EC to EFh.
The UPP module contains two address decoders: one for ensuring communication with the TNS (IO 9), i.e. resolving the addresses of the UPP module on the TNS bus, and the other (IO 8) for dividing the address space of the UPP itself. The first decoder (IO 9 – PROMka 745571) sets the standard addresses of the UPP-NET module in the range A0 to A3h. The second decoder (IO 8) is implemented by the 3205 circuit and divides the memory address space between the EPROM memory area, RAM and space
corresponding to the input and output buffer addresses in the TNS bus interface circuits, which are mapped to the memory space, i.e. UPP-NET reads and sends data to TNS using read and write operations in the memory.
= 2.2 Description of the connection of the UPP-NET application part =
The TxD data transmitted from the SIO in the rhythm of the transmitted transmission clock TxC is encoded in the SEEQ Manchester encoder, formed by the circuits IO 27, IO 28.A,B,D and IO 29.A. The coded signal is fed to the line transmitter, formed by a 75325 circuit, to the outputs of which a line excitation isolation transformer is connected.
The operation of the transmitter can be blocked by applying log.1 to the S2 input of the 74325 circuit. This blocking of the transmitter is necessary for the cooperation of several transmitters on the line and is controlled from the circuit of the hardware line occupant, formed by IO 31.A.
The receiver winding is also located on the line transformer. The receiver consists of a fast comparator, which has a hysteresis of about 100 mV set using positive feedback. There is a protection circuit at the input of the comparator. The output from the comparator is fed both to the Manchester decoder and to the monostable flip-flop IO 26.A with a time constant of about 50 μs, which serves as a line occupancy indicator and is read by the processor at input PA7 of the PIO circuit (gate A, bit 7).
Information about line occupancy is also provided to the HW line occupyer IO 31.A (if the line is occupied, our station can no longer occupy it) and to the WAIT signal generator, formed by IO 29.C and T1 (however, it is not used in the current software version).
The connection of the Manchester decoder is based on the solution of the SEEQ company and consists of circuits IO 23.A, IO 24, IO 25 and IO 30.C,D. The Z80-SIO circuit receives RxD data and RxC clock from the decoder.
The timing of all circuits is derived from a 10 MHz crystal oscillator formed by inverters. The frequencies for the operation of the delayers from the shift registers in the decoder and for controlling the encoder are derived from it after division.
With the address PROM, the UPP-NET board is addressed in the space 0A0H to 0A4H (see UPP-standard description).
The UPP-NET module does not require any jumper settings. The jumpers, which are standard on UPP boards (square solder pads), are scanned directly in the printed circuit on the UPP-NET application and are therefore fixed.
The UPP-NET module contains one "DIP-switch" with eight switches, six of which are used to set the address of the user station in the address range 0 to 3F in hexadecimal (i.e. a total of 64 stations) and the remaining two switches are locked. The least significant bit of the six-bit station address is set by a switch on the side of the DIP-switch case facing the TNS bus connector, i.e. on the key side of the IO case. In the direction from the DIP-switch case to the front with the connectors for the coaxial cable, there are successively switches of higher weight bits of the station address. At the same time, the open switch sets the bit to log.1 (the side marked on the DIP-switch with the number 0) and the closed switch gives log.0 (side 1).
= 4.1 Internal CPU ports on the UPP-NET module =
Circuit | Port | Functions ----------|-------|------------------------------------------------ CTC ch.0 | 0xF8 | CTC interrupt base vector (write 0x40 = base) CTC ch.1 | 0xF9 | Reset (CTC1, unused) CTC ch.2 | 0xFA | Reset (CTC2, unused) CTC ch.3 | 0xFB | Line pulse counter / interrupt generator for TNS write detection | | WR: 0xD7 = counter mode, rising edge, time const follows | | Time constant = 1 → interrupt after each pulse PIO AND data| 0xF4 | Read: bit7 = line busy (monostable 50 μs) | | bits 5:0 = station address from DIP switches PIO AND Management | 0xF6 | PIO gate A setting (mode 3 = bit mode, 0xFF = all input) PIO B data| 0xF5 | Bit 7 = transmitter blocking (1 = block) | | Bit 6 = TX enable (1 = TX enabled) | | Bit 5 = line busy status (1 = line free for TX) | | Bit 1 = data flag in TNS input buffer (for main loop) | | Bit 0 = TX/transmit status PIO B management | 0xF7 | Gate B PIO settings SIO A data| 0xEC | Read = received byte from network, Write = byte to transmit SIO A control.| 0xEE | SIO channel A status (read) / WRx commands (write) SIO B data| 0xED | (not used in network code) SIO B control.| 0xEF | SIO channel B WRx commands - setting the interrupt vector WR2
= 4.2 SIO ports key bits A control (0xEE) when read (RR0) =
Bit 0 (rrca → CF): RX Character Available Bit 1: Zero Count (CRC) Bit 2 (bit 2, a): TX Buffer Empty Bit 5 (bit 5, a): SYNC/HUNT (waits for SDLC flag) Bit 6 (bit 6, a): DCD (Data Carrier Detect / Line Active) CF after rlca: Corresponds to bit 7 = Break/Abort received
= 4.3 Standard UPP-NET addresses from the TNS bus side (host port) =
Address TNS | Hex | Functions -----------|------|------------------------------------------------ UPP input | 0xA0 | Write (TNS→UPP): destination node number (0-63) UPP status1 | 0xA1 | Reading input register status UPP output | 0xA2 | Read UPP output register (UPP→TNS) UPP status2 | 0xA3 | Reading the status of the output register
5. Shared SRAM map (view from host TNS)
The host TNS communicates with UPP-NET via a shared memory area mapped to
of the CPU Z80's own address space on the UPP card:
UPP CPU Address | Function (access from UPP CPU) ---------------|------------------------------------------------ 0x0000–0x0FFF | EPROM (firmware, read-only) 0x4000–0x4FFF | RAM (internal variables and buffers, see below) 0x5000–0x5FFF | Reading the input buffer (= what TNS wrote to address 0xA0) | Format: [target_node(1B)] then [length(1B)][data...] | Special values: 0x80 = UPP hard reset 0x6000–0x6FFF | Writing to the output buffer (UPP → TNS), WITHOUT activating -SI1 0x7000–0x7FFF | Writing to the output buffer (UPP → TNS), With activation of -SI1 | (TNS processor interrupt)
6. Internal RAM Layout 0x4000–0x43FF
Address | Length | Title | Description ------------|-------|------------------------|------------------------------------------ 0x4000–403F | 64 B | tx_seq_table | Table of TX sequence numbers (per node) | | | unk_4000[n] = next TX seq for node n | | | bit7=1: broadcast/special mode | | | initialization: 0x80 (uninitialized) 0x4040–407F | 64 B | rx_seq_table | Table of RX sequence numbers (per node) | | |