MHB1012
UART clone from Tesla, apparently compatible with AY-3-1015D.
In Czechoslovakia, for example, in the peripheral cards S2 and DAP at ZVT SP-800.
| PIN number | English name | abbreviation | Czech name | Function | |
| "1" | Power Supply | VCC | Power VCC | +5V power supply | |
| "2" | Power Supply | VGG | Power VGG | -12V Power | |
| "3" | Ground | vdi | ground | ground | |
| "4" | Received Data Enable | ||||
| "5-12" | Received Data Bits | RD8-RD1 | Received Data Bits | This is 8 output data lines. Received characters are aligned to the right: LSB always appears on RD1. These lines have three -state outputs; ie they have normal TTL characteristics in RDE = '0' and high impedance at RDE = '1'. Thus, data outputs can be oriented to the bus. | |
| "13" | Parity Error | PE | Parity Error Three -state output. | ||
| "14" | Framing Error | Fe | Framework | Received character has no valid Stop bit. Three -state output. | |
| "15" | Over-Run | OR | Overflow | This PIN goes to logical '1' | If the previously received character has not been read (the crowd has not been reset) before transferring the current character to the admission register. Three -state output. |
| "16" | Status Word Enable | SWE | Permitting Status Word | Logical '0' on this pin allows the transmission of status bits (P/Fe/OR/DP/TBMT) to the output lines. Three -state output. | |
| "17" | Clock receiver | RCP | Receiver clock | This PIN contains an hourly signal whose frequency is 16 times (16 ×) greater than the required transfer rate. | |
| "18" | Reset Data Available The only thing which is reset | is a crowd f/f. Must be attached to the logical '1' | |||
| "19" | Data Available When the whole character is accepted and transferred to the admission register. Three -state output. | ||||
| "20" | Serial Input | Si | Serial Input | This PIN receives a serial input current. Transition from logical '1' to logical '0' is required to start income. | |
| "21" | external reset | XR | external reset | reset all registers except the registry of the received data (not reset at AY-5-1013A and AY-6-1013). Sets SC, EOC and TBMT to logical '1'. Reset the crowd and error symptoms on '0'. Elutes the input data buffer. Must be connected to the logical '0' | If not used. |
| "22" | Transmitter Buffer Empty | TBMT | Empty Transmitter Buffer | The Empty Breeding Buffer flag goes to logical '1' when the sending data register is ready to record another character. Three -state output. | |
| "23" | Data Strobe | DS | Data Impulse " | " Impuls on this pin writes data bits to data storage register. The start of data transfer is initiated by the ascending edge of the DS. The data must be stable throughout the pulse duration. | |
| "24" | End of Character | EOC | End of character " | " This pin goes to logical '1' as soon as the entire character is transferred. Remains in this state until the transfer of another character is initiated. | |
| "25" | Serial Output | SO | Serial output " | " This pin provides a whole transmitted character. It remains in logical '1' when no data is transmitted. | |
| "26-33" | Data Bit Inputs | DB1-DB8 | data inputs " | " is available up to 8 input data bits. | |
| "34" | Control Strobe | CS | Control Impulse " | " Logical "1 'on this pin writes control bits (EPS, NB1, NB2, TSB, NP) to the data storage register. This PIN can be activated by an pulse or permanently connected to the logical '1'. | |
| "35" | No Parity | NP | No Parity " | " logic "1 'on this pin removes a parity bit from the transmitted and received character (a parity error will not be indicated). Stop bit (s) follow directly behind the last data bit. If it is not used, it must be connected to the logical '0'. | |
| "36" | Number of Stop Bits | TSB | Number of Bits " | " This pin determines the number of bits, 1 or 2, which connects behind a parity bit. Logical '0' inserts 1 STOP bit, logical '1' inserts 2 feet bits. U AY-3-1014A/1015 Combination of 2 feet bits and 5-bit character creates 1.5 feet of bits. | |
| "37-38" | Number of Bits/Character | NB2, NB1 | Number of Bits per character " | " These two pins internally decode to select 5, 6, 7 or 8 bits per character. | |
| "39" | ODD/event Parity Select | EPS | Selection of odd/even parity " | " logical level on this pin selects a type of parity that connects as data bits. It also determines the parity controlled by the receiver. Logical '0' inserts odd parity, logical '1' inserts a barrel of parity. | |
| "40" | Transmitter Clock | TCP | The Transmitter Hour Signal " | " This PIN contains an hourly signal with a frequency 16 times higher (16 ×) than the required transfer rate of the transmitter. |