74181

Obwód 74181 to 4-bitowy układ ALU.

Odpowiednik Verilog, nie zajmuje się przeprowadzaniem itp.:

moduł alu74181(
wejście [3:0]s,
wejście ci, M,
wejście [3:0] a, b,
moc wyjściowa [3:0] y
);

reg [3:0] p, g;

zawsze zaczynaj @(*).

p[0] <= ~(a[0] | (s[0] i b[0]) | (s[1] i ~b[0]));
p[1] <= ~(a[1] | (s[0] i b[1]) | (s[1] i ~b[1]));
p[2] <= ~(a[2] | (s[0] i b[2]) | (s[1] i ~b[2]));
p[3] <= ~(a[3] | (s[0] i b[3]) | (s[1] i ~b[3]));

g[0] <= ~((a[0] i ~b[0] i s[2]) | (a[0] i b[0] i s[3]));
g[1] <= ~((a[1] i ~b[1] i s[2]) | (a[1] i b[1] i s[3]));
g[2] <= ~((a[2] i ~b[2] i s[2]) | (a[2] i b[2] i s[3]));
g[3] <= ~((a[3] i ~b[3] i s[2]) | (a[3] i b[3] i s[3]));

y[0] = (p[0] ^ g[0]) ^ ~(~ci i ~M);
y[1] = (p[1] ^ g[1]) ^ ~((~ci & ~M i g[0]) | (~M i p[0]));
y[2] = (p[2] ^ g[2]) ^ ~((~ci & ~M i g[0] i g[1]) | (~M i p[1]) | (~M & p[0] & g[1]));
y[3] = (p[3] ^ g[3]) ^ ~((~ci & ~M i g[0] i g[1] i g[2]) | (~M i p[2] ) |. (~M i p[1] i g[2]) |. (~M i p[0] i g[1] i g[2]));
koniec
moduł końcowy // alu74181