Also called agroPUTER85.Designed by Ing. Petr Kotek, Ing. Jiří Filčev, CSc., ČVUT FEL, Jan Šedivý, K331 Katedra teorie obvodů.It was manufactured from 1988 by JZD ČSLA-VZLET.
Hardware is based on U880D.
Development of CTU
Production of JZD ČSLA-VZLET Nové Město na Moravá
Approximately 20-40 units were produced, because it was a relatively unsalable computer, most went straight to the bazaar as new.
C0 and C2 - activates the RAM control board (write) C1 and C3 - activates the controlled RAM board (write) C0 and C1 - suppresses the parity check C2 and C3 - releases the parity check
D0 - FDC status register D1 - FDC track register D2 - FDC sector register D3 - FDC data register D4 - PIO channel A Data D5 - PIO channel B Data D6 - PIO channel A control D7 - PIO channel B control D8 - CTC channel 0 D9 - CTC channel 1 DA - CTC channel 2 DB - CTC channel 3 DC - SIO channel A Data DD - SIO channel B Data DE - SIO channel A control DF - SIO channel B control
EC - DMA F0 - PIO channel A Data F1 - PIO channel B Data F2 - PIO channel A control F3 - PIO channel B control F4 - CTC channel 0 F5 - CTC channel 1 F6 - CTC channel 2 F7 - CTC channel 3 F8 - SIO channel A Data F9 - SIO channel B Data FA - SIO channel A control FB - SIO channel B control FC - PSK Site selection register -> bit function specifies page address 0.1 AR16,AR17 in memory read cycle 2,3 AW16,AW17 in the memory write cycle 4.5 AM16,AM17 in the operation code reading cycle in 6 --- not used 7 /MONITOR log.0 activates the monitor memories