Vzlet Z256

Contents
CTU development
Production of JZD Čsla-Vzlet Nové Město na Moravě
Made by an estimate of about 20-40pcs, because it was a relatively unsalable computer, most went as new straight to the bazaar.
- CPU
- Also applicable independently outside of the 256 assembly
- connectors: bus A1 FRB62 / Paralell B1 FRB30 / UART C1 FRB20
- RAM
- connectors: bus A1 FRB62
- FTCB
- connectors: bus A1 FRB62 FDC B2 FRB30 / UART / MGF C2 FRB20 / D1 FRB20 keyboard
- CRTC (uses MC6845 or its clones)
- Connectors: bus A1 FRB62 / VIDEO B3 FRB20 Connection to Mercury's modified monitor, interesting is that it uses CRTC timing and video signal to the maximum.
C0 and C2 - activates RAM control plate (write) C1 and C3 - activates the RAM controlled board (writing) C0 and C1 - suppresses parity control C2 and C3 - releases parity control
FDC
D0 - FDC status register D1 - FDC register of tracks D2 - FDC register of sector D3 - FDC Data Register D4 - PIO channel and data D5 - Pio channel B data D6 - Pio channel and driving D7 - PIO channel B control D8 - CTC channel 0 D9 - CTC channel 1 Da - CTC channel 2 Db - CTC channel 3 DC - SIO channel and data DD - SIO channel B data DE - SIO channel and driving DF - SIO channel B driving
cpu
EC - DMA F0 - PIO channel and data F1 - Pio channel B data F2 - Pio channel and driving F3 - PIO channel B control F4 - CTC channel 0 F5 - CTC channel 1 F6 - CTC channel 2 F7 - CTC channel 3 F8 - SIO channel and data F9 - SIO channel B data FA - SIO channel and driving FB - SIO channel B driving FC - PSK Register of Page Choice -> Bit Function determines the address of the page 0.1 AR16, AR17 in the Reading Cycle 2,3 AW16, AW17 in a memory writing cycle 4.5 AM16, AM17 in the cycle Reading code in IN 6 --- not used 7 /Monitor Log.0 activates monitor memories
Inaccuracies/doubts related to the topic
Uncertain alternate name or production years. Necessary to find out from period documents.