74181
IC 74181 ist 4-Bit-Alu.
| Richtung | Breite | Name | Beschreibung | |
| Eingabe | [3: 0] | a | Eingabe a | |
| Eingabe | [3: 0] | B | Eingabe b | |
| Eingabe | [3: 0] | S | Ausgewählte Funktion | |
| Eingabe | M | Modus: 0 = Logic | 1 = Arithmetik | |
| Eingabe | Cn | Übertragung | ||
| Ausgabe | [3: 0] | f | Ergebnis | |
| Ausgabe | X | Erzeugen | ||
| Ausgabe | Y | Propagieren Sie sich | ||
| Ausgabe | Aeqb | A == b | ||
| Ausgabe | CNP4-Übertragung (CN+4) |
| S3 | S2 | S1 | S0 | Logikfunktion | logische Beschreibung | Arith -Funktion | Arith Beschreibung | |
| - | - | - | - | -------------------- | ------------------------ | ------------------------------ | --------------------- | |
| 0 | 0 | 0 | 0 | ! (A | b) | oder | A | übertragen a | |
| 0 | 0 | 0 | 1 | ! (A & b) | nand | a +! B | a - b - 1 | |
| 0 | 0 | 1 | 0 | ! A & B | nicht a und b | a +! B + cn | a - b | |
| 0 | 0 | 1 | 1 | ! A | nicht a | a - 1 + cn | a - 1 | |
| 0 | 1 | 0 | 0 | ! B | nicht b | a + a | doppelte a | |
| 0 | 1 | 0 | 1 | a ^ b | xor | a + a +! B | a + a - b - 1 | |
| 0 | 1 | 1 | 0 | ! A | B | nicht a oder b | a + a +! B + cn | a + a - b | |
| 0 | 1 | 1 | 1 | ! (A ^ b) | xnor | 2a - 1 + cn | double a minus 1 | |
| 1 | 0 | 0 | 0 | a & b | und | a + b | hinzufügen | |
| 1 | 0 | 0 | 1 | ! (A |! B) | oder mit nicht b | a + b + 1 | mit Tragen hinzufügen | |
| 1 | 0 | 1 | 0 | A | A | a + 1 | Inkrement a | |
| 1 | 0 | 1 | 1 | A | ! B | a oder nicht b | a +! B + 1 | a - b + 1 | |
| 1 | 1 | 0 | 0 | B | Übertragung b | 1 | immer 1 (eingestellt) | |
| 1 | 1 | 0 | 1 | A | B | oder | 0 | immer 0 (klar) | |
| 1 | 1 | 1 | 0 | a &! B | a und nicht b | ! B | nicht b | |
| 1 | 1 | 1 | 1 | ! (A ^ b) | xnor | ! B + cn | nicht b + carry |
Verilogäquivalent, ohne Trage und andere wichtige Signale:
Modul Alu74181 (
Eingabe [3: 0] s,
Eingabe ci, m,
Eingabe [3: 0] a, b,
Ausgabe Reg [3: 0] y
);
Reg [3: 0] p, g;
Immer @(*) Beginnen Sie
p [0] <= ~ (a [0] | (s [0] & b [0]) | (s [1] & ~ B [0]);
P [1] <= ~ (a [1] | (S [0] & B [1]) | (S [1] & ~ B [1]);
P [2] <= ~ (A [2] | (S [0] & B [2]) | (S [1] & ~ B [2]);
P [3] <= ~ (A [3] | (S [0] & B [3]) | (S [1] & ~ B [3]);
g [0] <= ~ ((a [0] & ~ B [0] & s [2]) | (a [0] & b [0] & s [3]));
g [1] <= ~ ((a [1] & ~ B [1] & s [2]) | (a [1] & b [1] & s [3]);
g [2] <= ~ ((a [2] & ~ B [2] & s [2]) | (a [2] & b [2] & s [3]));
g [3] <= ~ ((a [3] & ~ B [3] & s [2]) | (a [3] & b [3] & s [3]);
y [0] = (p [0] ^ g [0]) ^ ~ (~ ci & ~ m);
y [1] = (p [1] ^ g [1]) ^ ~ ((~ ci & ~ m & g [0]) | (~ m & p [0]));
y [2] = (p [2] ^ g [2]) ^ ~ ((~ ci & ~ m & g [0] & g [1]) | (~ m & p [1]) | (~ m & p [0] & g [1]);
y [3] = (p [3] ^ g [3]) ^ ~ ((~ Ci & ~ M & g [0] & g [1] & g [2]) | (~ m & p [2]) | (~ m & p [1] & g [2]) | (~ M & p [0] & g [1] & g [2]);
Ende
endmodule // alu74181
Vervollständigen Sie Verilog, noch nicht überprüft:
Modul Alu74181 (
Eingangsdraht [3: 0] a,
Eingangsdraht [3: 0] b,
Eingangsdraht [3: 0] s,
Eingangsdraht m, // Modus: 0 = Logik, 1 = Arithmetik
Eingangsdraht CN, // Übertragung
Ausgangsdraht [3: 0] f, // Ergebnis
Ausgangsdraht x, // tragen erzeugen
Ausgangsdraht y, // Propagate tragen
Ausgangsdraht AEQB, // a == b
Ausgangsdraht CNP4 // Carry-out (CN+4)
);
Draht [3: 0] Tu;
Draht [3: 0] TV;
Kabel [3: 0] TX;
// tu [n] = ~ (a [n] | (b [n] & s [0]) | (~ b [n] & s [1]))
zuweisen tu [0] = ~ (a [0] | (b [0] & s [0]) | (~ b [0] & s [1]));
TU [1] = ~ (a [1] | (b [1] & s [0]) | (~ b [1] & s [1]) zuweisen;
TU [2] = ~ (a [2] | (b [2] & s [0]) | (~ B [2] & s [1]));
zuweisen tu [3] = ~ (a [3] | (b [3] & s [0]) | (~ b [3] & s [1]));
// tv [n] = ~ ((a [n] & ~ b [n] & s [2]) | (a [n] & b [n] & s [3]))
TV [0] = ~ ((a [0] & ~ B [0] & s [2]) | (a [0] & b [0] & s [3]));
TV [1] = ~ ((a [1] & ~ B [1] & s [2]) | (a [1] & b [1] & s [3]));
TV [2] = ~ ((a [2] & ~ B [2] & s [2]) | (a [2] & b [2] & s [3]));
TV [3] = ~ ((a [3] & ~ B [3] & s [2]) | (a [3] & b [3] & s [3]));
// tx [n] = tu [n] ^ tv [n]
TX = TU ^ TV zuweisen;
// Ty = Tu0 & TV1 & TV2 & TV3 | TU1 & TV2 & TV3 | Tu2 & TV3 | Tu3
Wire Ty = (Tu [0] & TV [1] & TV [2] & TV [3]) |
(TU [1] & TV [2] & TV [3]) |
(TU [2] & TV [3]) |
Tu [3];
// f [n] = tx [n] ^ Logik tragen
zuweisen f [0] = tx [0] ^ ~ (m & cn);
zuweisen f [1] = tx [1] ^ ~ ((tu [0] & m) | (tv [0] & m & cn));
zuweisen Sie f [2] = tx [2] ^ ~ ((tu [1] & m) |
(Tu [0] & TV [1] & m) |
(TV [0] & TV [1] & m & cn));
ordnen Sie f [3] = tx [3] ^ ~ ((tu [2] & m) | zu
(TU [1] & TV [2] & M) |
(Tu [0] & TV [1] & TV [2] & M) |
(TV [0] & TV [1] & TV [2] & m & cn));
// Statusausgänge
zuweisen x = ~ (tv [0] & tv [1] & tv [2] & tv [3]); // Carry erzeugen (g)
y = ~ ty zuweisen; // Propagate tragen (p)
ordnen aeqb = f [0] & f [1] & f [2] & f [3]; // a == b
zuweisen Sie CNP4 = ty | (TV [0] & TV [1] & TV [2] & TV [3] & CN); // Carry-out (CN+4)
Endmodule