2. Introduction to ARM7TDMI core

The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macrocell optimized to provide the best combination of performance, power and area characteristics. The ARM7TDMI core enables system designers to build embedded devices requiring small size, low power and high performance.

2.1 ARM7TDMI Features

• 32/16-bit RISC architecture (ARM v4T)
• 32-bit ARM instruction set for maximum performance and flexibility
• 16-bit Thumb instruction set for increased code density
• Unified bus interface, 32-bit data bus carries both instructions and data
• Three-stage pipeline
• 32-bit ALU
• Very small die size and low power consumption
• Fully static operation
• Coprocessor interface
• Extensive debug facilities (EmbeddedICE debug unit accessible via JTAG interface unit)

2.2 Benefits

• Generic layout can be ported to specific process technologies
• Unified memory bus simplifies SoC integration process
• ARM and Thumb instructions sets can be mixed with minimal overhead to support application requirements for speed and code density
• Code written for ARM7TDMI-S is binary-compatible with other members of the ARM7 Family and forwards compatible with ARM9, ARM9E and ARM10 families, thus it's quite easy to port your design to higher level microcontroller or microprocessor
• Static design and lower power consumption are essential for battery -powered devices
• Instruction set can be extended for specific requirements using coprocessors
• EmbeddedICE-RT and optional ETM units enable extensive, real-time debug facilities